https://www.theregister.co.uk/2018/11/05/sk_hynix_96_layer_flash_chip/

SK Hynix has finished work on a 512 Gbit, 96-layer, 3D NAND chip with 1Tbit, and 3bits/cell (TLC) and 4bits/cell (QLC) coming later.

Currently SK Hynix is shipping 72-layer 3D NAND chips. The 96-layer chip uses charge trap flash (CTF) tech, as opposed to floating gate, and its logic circuitry is placed underneath the flash cells. SK Hynix calls this Periphery Under Cell (PUC) tech, and it follows what rivals are doing – all building physically smaller chips as a result.